TSMC tandem builds exotic new MRAM-based memory with radically lower latency and power consumption

TSMC and Taiwan’s Industrial Technology Research Institute (ITRI) on Thursday announced that they had jointly developed co-developed a spin-orbit-torque magnetic random-access memory (SOT-MRAM) array chip, the result of a joint development program the tandem announced in 2022. The memory device can be used for computing in memory architectures and last-level cache, boasting non-volatility, low latencies, and power consumption that is 1% of that of spin-transfer torque (STT) MRAM.

In theory, SOT-MRAM has numerous advantages that make it usable for caches and in-memory applications. SOT-MRAM can potentially offer higher density than SRAM, which barely scales with the latest production technologies. Being non-volatile, it also consumes no power when not in use (unlike SRAM), which is beneficial both for data center and battery-power applications. SOT-MRAM is theoretically capable of latencies up to 10ns, which is certainly slower compared to SRAM (read and write latency of SRAM is typically in the range of 1-2ns), but is slightly faster than DRAM (DDR5 has latency around 14ms) and considerably faster than 3D TLC NAND (which has read latencies between 50 and 100 microseconds). 

“This unit cell achieves simultaneous low power consumption and high-speed operation, reaching speeds as rapid as 10ns,” said Dr. Shih-Chieh Chang, General Director of Electronic and Optoelectronic System Research Laboratories at ITRI. “Its overall computing performance can be further enhanced when integrated with computing in memory circuit design. Looking ahead, this technology holds the potential for applications in high-performance computing (HPC), artificial intelligence (AI), automotive chips, and more.” 

Spin-orbit-torque magnetic random-access memory (SOT-MRAM) and spin-transfer torque (STT) MRAM are types of non-volatile memory technology that uses magnetic states to store data. In both SOT and STT MRAM, the memory cell relies on a structure called a magnetic tunnel junction (MTJ) that comprises a free and a fixed thin magnetic layer (e.g., CoFeB) stacked vertically with a very thin dielectric layer (e.g., MgO) sandwiched between them, and an additional ‘heavy metal’ (e.g., Tungsten) layer adjacent to one of the magnetic layers.  

Data is written to the memory cell by changing the magnetization in the free layer (which acts as the ‘storage’ layer in the MRAM bit cell) by passing a current through the heavy metal layer, which generates a spin current and injects it into the adjacent magnetic layer, switching its orientation and thus changing its state. Reading data involves assessing the magnetoresistance of the MTJ by directing a current through the junction. The main difference between STT- and SOT-MRAM resides in the current injection geometry used for the write process, and apparently, the SOT method ensures lower power consumption and device longevity.  

While SOT-MRAM offers lower standby power than SRAM, it needs high currents for write operations, so its dynamic power consumption is still quite high. Furthermore, SOT-SRAM cells are still larger than SRAM cells, and they are harder to make. As a result, while the SOT-SRAM technology looks promising, it is unlikely that it will replace SRAM any time soon. Yet, for in-memory computing applications, SOT-MRAM could make a lot of sense, if not now, but when TSMC learns how to make SOT-MRAM cost-efficiently.